As semiconductor technologies continue to increase the speed at which ICs operate, at-speed functional testing at both the IC and circuit board level becomes more difficult. Traditionally, circuit boards are tested at-speed using functional test equipment. Functional testers input test patterns to a board's primary inputs and measure the response from the board's primary outputs. If the primary outputs do not match the expected response the functional test fails. The cost to purchase or design high speed functional testers capable of keeping up with state-of-the-art board design is rapidly escalating.
With the recent announcement of the IEEE 1149.1 boundary scan standard, more ICs designs will include boundary scan as a method to improve board level testability. The 1149.1 standard describes a test architecture that can be designed into ICs to facilitate testing of wiring interconnects between ICs in a circuit.
The 1149.1 architecture comprises a test access port (TAP) and a series of scannable boundary test cells, one cell per input and output signal. The input test cells are combined into an input test cell register (TCR1) and the output test cells are combined into an output test cell register (TCR2).
The 1149.1 standard provides an instruction, referred to as external test (Extest) which places the IC in an off-line non-functional test mode and allows the IC's output pins to be controlled by TCR2, while the input pins are observable via TCR1. This instruction allows the wiring interconnects as well as combinational logic between ICs on a board design to be easily tested by repetitive scan access operation to TCR1 and TCR2.
In addition, the 1149.1 standard provides an instruction, referred to as Sample, which allows the ICs boundary scan path to be accessed while the IC is in an on-line functional mode. In response to control input to the TAP, the Sample instruction captures the data entering and leaving the IC in TCR1 and TCR2 then shifts it out for inspection. This test does not affect the operation of the IC.
The Sample instruction, however, has several limitations. One problem involves synchronizing the control inputs so that data can be sampled while in a stable state, not in a transitioning state. Another problem with the Sample instruction involves qualifying when the boundary data is to be sampled. In order to obtain meaningful data the sample operation should be qualified by the occurrence of an expected event. Sampling data synchronously, but at random has limited practical applications in system testing.
Still another problem with the Sample instruction is that the same control signals are routed globally to each IC on a board design to allow shifting data through all ICs during scan operations. Since each IC receives the same control signals, the data sample operation must be applied globally across all IC boundaries. In typical board designs not all ICs operate on the same system clock, therefore it is impossible to obtain valid data from all IC boundaries with one sample operation.
Therefore, a need has arisen for a circuit design which will allow the board level functional testing to be performed by test logic in the IC's themselves, rather than by external test equipment. Further, the test circuitry should sample data in a stable state, respond to qualifying events, and should operate with separate system clocks.